SynaptiCAD is now the US and Canadian distributor for HDL Works EDA tools: Ease, HDL Companion, and IO Checker. These tools provide alternative graphical approaches for VHDL and Verilog code design ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added a customizable tool qualification data ...

Active-HDL suggests an early-bug-detection flow via the integration with ALINT-PRO. The Active-HDL user has an access to both different linting methodologies supported by ALINT-PRO: full chip-level ...

Mentor Graphics released a new concurrent design checking and creation environment for FPGA and ASIC design teams working with Verilog, SystemVerilog, and VHDL design languages. The capability is ...

As design size and complexity grows, the design verification effort grows even more. It takes significant amount of time to thoroughly verify complex control logic of a design, which is the key and ...